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4 - channel , i 2 c , ultralow power, 12 - bit adc in 20 - lead lfcsp/tssop data sheet ad7091r - 5 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subect to chang e without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 020 62 - 9106, u.s.a. tel: 781.329.4700 2015 analog devices, inc. all rights reserved. technical support www. analog.com features i 2 c - compatible serial interface supports standard and fast modes ultralow power: 90 w typical at 3 v in fast mode specified for v dd of 2.7 v to 5.25 v on - chip accurate 2.5 v r eference, 5 ppm/ c typical drift 4 single - ended analog input channels alert function busy function autocycle mode wide input bandwidth 68 db signal - to - noise ratio ( snr ) typical at input frequency of 1 khz flexible power/throughput rate management no pipeline delays power - down m ode 550 na typical at v dd = 5.25 v 435 na typical at v dd = 3 v 20- lead lfcsp and ts sop p ackages temperature range: ? 40 c to +125c applications battery - powered systems personal digital assistants medical i nstruments mobile c ommunications instrumentation and control systems data acquisition syste ms optical s ensors diagnostic/monitoring functions functional block dia gram input mux channel sequencer control logic i 2 c interface t/h reset convst/gpo 1 sda scl as 0 as 1 v drive v in 0 mux out adc in v dd ref in / ref out regcap alert/busy/ gpo 0 gpo 2 gnd gnd v in 1 v in 2 v in 3 12-bit successive approximation adc on-chip osc 2.5v vref ad7091r-5 12093-001 figure 1. general description the ad7091r - 5 is a 1 2 - bit, multichannel , ultra low powe r, succes - sive approximation analog - to - digital converter ( adc ) . the ad7091r - 5 operates from a single 2.7 v to 5.25 v power supply and typically consumes only 24 a at a 3 v supply in f ast mode . the ad7091r - 5 provides a 2 - wire serial interface compatible with i 2 c interfaces. the conversion process can be controlled by a sam ple mode via the convst /gpo 1 pin , an autocycle mode selected through software control , or a command mode in which conversions occur across i 2 c write operations . the device contains a wide bandwidth track - and - hold amplifier that can handle input frequencies up to 1.5 mhz. the ad7091r - 5 also features an on - chip conversion clock, an on - chip accurate 2.5 v reference , and a programmable out of bounds user alert function . the ad7091r - 5 offers four single - ended analog input channels with a channel sequencer that allows a preprogrammed selection of channels to be converted sequentially. the ad7091r - 5 use s advanced design techniques to achieve ultra lo w power dissipation without compromising performance . it also feature s flexible power management options. an on - chip c onfiguration register allows the user to set up different operating con ditions. these includ e power management, alert functionality, busy indication, channel sequencing , and general - purpose output pins . the mux out and adc in pins allow signal conditioning of the multiplexer output before acquisition by the adc .
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ad7091r-5 data sheet rev. 0 | page 2 of 34 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing specifications ............................................................ 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 9 terminology .................................................................................... 14 theory of operation ...................................................................... 15 circuit information .................................................................... 15 converte r operation .................................................................. 15 adc transfer function ............................................................. 15 reference ..................................................................................... 15 power supply ............................................................................... 16 device reset ................................................................................ 16 analog input ............................................................................... 16 driver amplifier choice ............................................................ 17 typical connection diagram .................................................... 17 i 2 c registers .................................................................................... 19 addressing reg isters .................................................................. 19 slave address ............................................................................... 19 i 2 c register access ..................................................................... 19 conversion result register ....................................................... 20 channel register ........................................................................ 21 configuration register .............................................................. 22 alert indication register ........................................................... 24 channel x low limit register .................................................. 26 channel x high limit register ................................................. 26 channel x hysteresis register .................................................. 26 i 2 c interface .................................................................................... 27 serial bus address byte ............................................................. 27 general i 2 c timing .................................................................... 27 writing to the ad7091r -5 ............................................................ 28 writing two bytes of data to a 16 - bit register ..................... 28 writing to multiple registers .................................................... 28 reading data from the ad7091r -5 ............................................. 29 reading two bytes of data from a 16 - bit register ............... 29 modes of operation ....................................................................... 30 sample mode ............................................................................... 30 command mode ........................................................................ 30 autocycle mode .......................................................................... 32 power - down mode .................................................................... 32 alert ............................................................................................. 33 busy .............................................................................................. 33 channel sequencer .................................................................... 33 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 7/15r evision 0: initial version
data sheet ad7091r-5 rev. 0 | page 3 of 34 specifications v dd = 2.7 v to 5.25 v, v drive = 1. 8 v to 5.25 v, f scl = 400 khz, fast scl mode, v ref = 2.5 v internal/external, t a = ?40c to +125c, unless otherwise noted . table 1. parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave signal -to - noise ratio (snr) 68 db signal - to - noise - and - distortion ratio (sinad) 67 db total harmonic distortion (thd) ?80 db spurious - free dynamic range (sfdr) ?81 db channel to channel isolation ? 105 db aperture delay 5 ns aperture jitter 40 ps full power bandwidth at ?3 db 1.5 mhz at ?0.1 db 1.2 mhz dc accuracy resolution 12 bits integral nonlinearity (inl) ?1.25 0.8 +1.25 lsb differential nonlinearity (dnl) guaranteed no missing codes to 12 bits ?0.9 0.3 +0.9 lsb offset error t a = 25c ?1.5 0.3 +1.5 mv offset error matching t a = 25c ?1.5 0.3 +1.5 mv offset error drift 2 ppm/c gain error t a = 25c ?0.1 0.0 +0.1 % fs gain error matching t a = 25c ?0.1 0.0 +0.1 % fs gain error drift 1 ppm/c analog input input voltage range 1 at adc in 0 v ref v dc leakage current ?1 +1 a input capacitance 2 during acquisition phase 10 pf outside acquisition phase 1.5 pf multiplexer on resistance v dd = 5.0 v 50 ? v dd = 2.5 v 100 ? voltage reference input/output ref out 3 internal reference output, t a = 25c 2.49 2.5 2.51 v ref in 3 external reference input 1.0 v dd v drift 5 ppm/c power - on time c ref = 2.2 f 50 ms logic inputs input voltage high (v ih ) 0.7 v drive v low (v il ) 0.3 v drive v input current (i in ) v in = 0 v or v drive ?1 0.01 +1 a logic outputs output voltage high (v oh ) i source = 200 a v drive ? 0.2 v low (v ol ) i sink = 200 a 0.4 v floating state leakage current ?1 +1 a output coding straight (natural) binary
ad7091r-5 data sheet rev. 0 | page 4 of 34 parameter test conditions/comments min typ max unit conversion rate conversion time 550 ns update rate autocycle setting 00 90 100 110 s autocycle setting 01 180 200 220 s autocycle setting 10 360 400 440 s autocycle setting 11 720 800 880 s throughput rate f scl = 400 khz, command mode 22.22 ksps power requirements v dd 2.7 5.25 v v drive range 1.8 5.25 v i dd v in = 0 v normal mode static v dd = 5.25 v 22 50 a v dd = 3 v 21.6 46 a normal mode operational v dd = 5.25 v, f scl = 400 khz 26 55 a v dd = 3 v, f scl = 400 khz 24 52 a v dd = 5.25 v, f scl = 100 khz 25 54 a v dd = 3 v, f scl = 100 khz 23 51 a v dd = 3 v, autocycle mode 70 105 a power - down mode v dd = 5.25 v 0.550 17 a v dd = 5.25 v, t a = ?40c to +85c 0.550 8 a v dd = 3 v 0.435 15 a i drive v in = 0 v normal mode static v drive = 5.25 v 2 4 a v drive = 3 v 1 3.5 a normal mode operational v drive = 5.25 v, f scl = 400 khz 6 15 a v drive = 3 v, f scl = 400 khz 5 14 a v drive = 5.25 v, f scl = 100 khz 5 14 a v drive = 3 v, f scl = 100 khz 4 13 a total power dissipation 4 v in = 0 v normal mode static v dd = v drive = 5.25 v 130 290 w v dd = v drive = 3 v 70 150 w normal mode operational v dd = v drive = 5.25 v, f scl = 400 khz 170 370 w v dd = v drive = 3 v, f scl = 400 khz 90 200 w v dd = v drive = 5.25 v, f scl = 100 khz 160 360 w v dd = v drive = 3 v, f scl = 100 khz 85 195 w v dd = v drive = 3 v, autocycle mode 210 315 w power - down mode v dd = 5.25 v 3 95 w v dd = 5.25 v, t a = ?40c to +85c 3 33 w v dd = v drive = 3 v 1.4 50 w 1 the multiplexer input voltage must not exceed v dd . 2 sample tested during initial release to ensure compliance. 3 when referring to a single function of a multifunction pin in the parameters, only the portion of the pin name that is releva nt to the specification is listed. for full pin names of multifunction pins, see the pin configurations and function descriptions s ection. 4 total power dissipation includes contributions from v dd , v drive , and ref in (see note 3 ).
data sheet ad7091r- 5 rev. 0 | page 5 of 34 i 2 c timing specificati ons all values measured with the input filtering enabled. c b refers to the capacit ive load on the bus line, with rise time and fall time measured between 0.3 v drive and 0.7 v drive (see figure 2 ). v dd = 2 .7 v to 5.25 v , v drive = 1. 8 v to 5.25 v , v ref = 2.5 v internal/external , t a = t min to t max , unless otherwise noted. table 2 . limit at t min , t max parameter min typ max unit description f scl 100 khz serial clock frequency , s tandard mode 400 khz fast mode t 1 4 s scl high time , s tandard mode 0.6 s fast mode t 2 4.7 s scl low time , s tandard mode 1.3 s fast mode t 3 250 ns d ata setup time , s tandard mode 100 ns fast mode t 4 1 0 3.45 s d ata hold time , s tandard mode 0 0.9 s fast mode t 5 4.7 s s etup time for a repeated start condition , s tandard mode 0.6 s fast mode t 6 4 s h old time for a repeated start condition , s tandard mode 0.6 s fast mode t 7 4.7 s b us -fr ee time between a stop and a start condition , s tandard mode 1.3 s fast mode t 8 4 s s etup time for a stop condition , s tandard mode 0.6 s fast mode t 9 1000 ns r ise time of the sda signal , s tandard mode 20 + 0.1c b 300 ns fast mode t 10 300 ns f all time of the sda signal , s tandard mode 20 + 0.1c b 300 ns fast mode t 11 1000 ns r ise time of the scl signal , s tandard mode 20 + 0.1c b 300 ns fast mode t 11a 1000 ns r ise time of the scl signal after a repeated; not shown in figure 2 , s tandard mode 20 + 0.1c b 300 ns s tart condition and after an acknowledge bit , f ast mode t 12 300 ns f all time of the scl signal , s tandard mode 20 + 0.1c b 300 ns fast mode t sp 0 50 ns pulse width of the suppressed spike; not shown in figure 2 , f ast mode t reset pw 10 ns reset p ulse w idth (see figure 35) t reset_delay 50 ns reset pulse delay upon power - up (see figure 35) 1 a device must provide a data hold time for sda to bridge the undefined region of the scl falling edge . t 6 t 7 t 2 t 11 t 4 t 1 t 12 t 10 t 5 t 9 t 6 t 3 t 8 scl s sda s = start condition p = stop condition p p s 12093-002 figure 2. 2 - wire serial interface timing diagram
ad7091r- 5 data sheet rev. 0 | page 6 of 34 absolute maximum rat ings t a = 25c, unless otherwise noted . table 3 . parameter rating v dd to gnd ?0.3 v to +7 v v drive to gnd ?0.3 v to +7 v analog input voltage to gnd ?0.3 v to v ref + 0.3 v digital input 1 voltage to gnd ?0.3 v to v drive + 0.3 v digital output 2 voltage to gnd ?0.3 v to v drive + 0.3 v input current to any pin except supplies 3 10 ma operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150c esd human body model (hbm) 1.5 kv field induced charged device model (ficdm) 500 v 1 the digital input pins include the following: as 0 , reset , as 1 , scl, sda, and convst /gp o 1 . 2 the digital output pins inclu de: alert/busy/gpo 0 , gpo 2 , and sda . 3 transient currents of up to 100 ma do not cause scr latch - up. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. op eration beyond the maximum operating conditions for extended periods may affect product reliability . thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 4 . thermal resistance package type ja jc unit 20- lead lfcsp _wq 52 6.5 c/w 20 - lead tssop 84. 3 18.4 c/w esd caution
data sheet ad7091r- 5 rev. 0 | page 7 of 34 pin configuration s and function descrip tions ad7091r-5 top view (not to scale) 1 2 3 4 5 6 7 8 9 10 reset v dd regcap mux out gnd ref in /ref out as 0 alert/busy/gpo 0 v in 2 v in 0 20 19 18 17 16 15 14 13 12 11 convst/gpo 1 scl sda adc in gnd as 1 gpo 2 v in 3 v in 1 v drive 12093-004 figure 3. pin configuration, 20 - lead tssop notes 1. exposed pad. the exposed pad is not connected internally. it is recommended that the pad be soldered to gnd. 14 13 12 1 3 4 as 1 15 sda gnd adc in 11 v in 1 v dd ref in /ref out 2 regcap gnd 5 mux out 7 v in 2 6 v in 0 8 alert/busy/gpo 0 9 gpo 2 10 v in 3 19 as 0 20 reset 18 v drive 17 convst/gpo 1 16 scl ad7091r-5 top view (not to scale) 12093-003 figure 4. pin configuration, 20 - lead lfcsp table 5 . pin function descriptions pin no. mnemonic description tssop lfcsp 1 19 as 0 i 2 c a ddress b it 0 . together with as 1 , the logic state of these two inputs selects a unique i 2 c address for the ad7091r -5 . the device address depends on the logic state of these pins. 2 20 reset reset. logic input. this pin r esets the device when pulled low. 3 1 v dd power supply input. the v dd range is from 2.7 v to 5.25 v. decouple this supply pin to gnd. 4 2 regcap decoupling capacitor pin for voltage output from the internal regulator. decouple this output pin separately to gnd using a 2.2 f capacitor. 5 3 ref in /ref out volt age reference output, 2.5 v. decouple this pin to gnd. t he t ypical recommended decoupling capacitor value is 2.2 f. the user can either access the internal 2.5 v reference or overdrive the internal reference with the voltage applied to this pin. the refer ence voltage range for an externally applied reference is 1.0 v to v dd . 6, 15 4, 13 gnd chip ground pins. these pins are the ground reference point for all circuitry on the ad7091r - 5 . 7 5 mux out multiplexer output. the output of the multiplexer appears at this pin. if no external filtering or buffering is required, tie this pin directly to the adc in pin; otherwise, tie the output of the conditioning network to the adc in pin. 8 6 v in 0 analog input for channel 0. single - ended analog input. the analog input range is 0 v to v ref . 9 7 v in 2 analog input for channel 2. single - ended analog input. the analog input range is 0 v to v ref . 10 8 alert/busy/gpo 0 this is a multifunction pin determined by the configuration register. alert output pin (alert). when functioning as alert, this pin is a log ic output indicating that a conversion result has fallen outside the limit of the register settings. b usy o utput (busy). the busy pin indicate s when a conversion is taking place. general - purpose digital output 0 (gp o 0 ). 11 9 gpo 2 general - purpose digital output 2. 12 10 v in 3 analog input for channel 3. single - ended analog input. the analog input range is 0 v to v ref . 13 11 v in 1 analog input for channel 1. single - ended analog input. the analog input range is 0 v to v ref . 14 12 adc in adc input. this pin allows direct access to the adc. if no external filtering or buffering is required, tie this pin directly to the mux out pin; otherwise, tie the input of the conditioning network to the mux out pin.
ad7091r-5 data sheet rev. 0 | page 8 of 34 pin no. mnemonic description tssop lfcsp 16 14 as 1 i 2 c a ddress b it 1 . together with as 0 , the logic state of these two inputs selects a unique i 2 c address for the ad7091r -5 . the device address de pends on the logic state of these pins. 17 15 sda serial data input/output . this open - drain output requires a pull - up resistor. the outp ut coding is straight binary for the voltage channels. 18 16 scl digital input serial i 2 c bus clock. this input requires a pull - up resistor . the data transfer rate in i 2 c mode is compatible with both 100 khz (standard mode) and 400 khz (fast mode) operating modes. 19 17 convst /gpo 1 this is a m ultifunction pin determined by the configuration register and mode of conversion. convert start input signal ( convst ). e dge triggered logic input. the falling edge of convst places the adc into hold mode and initiates a conversion. the logic level of c onvst at eoc controls the power modes of the ad7091r -5 . general - purpose digital output 1 (gpo 1 ). w hen in command or autocycle mode, this pin can function as a general - purpose digital output. 20 18 v drive logic power supply input. the voltage supplied at this pin determines at what voltage the in terface operates. connect decoupling capacitors between v drive and gnd. t he t ypical recommended values are 10 f and 0.1 f. the voltage range on this pin is 1.8 v to 5.25 v and may differ from the voltage range at v dd , but must never exceed it by more than 0.3 v. n /a 1 21 epad exposed pad. the exposed pad is not connected internally. it is recommended that the pad be soldered to gnd. 1 n/a means not applicable.
data sheet ad7091r- 5 rev. 0 | page 9 of 34 typical performance characteristics 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 inl (lsb) code v dd = 3.0v v ref = 2.5v f scl = 400khz t a = 25c positive inl = +0.43 lsb negative inl = ?0.66 lsb 0 512 1024 1536 2048 2560 3072 3584 4095 12093-205 figure 5 . integral nonlinearity vs. code 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 inl (lsb) reference input voltage (v) min inl (lsb) max inl (lsb) v dd = 5.25v v ref = external f scl = 400khz t a = 25c 12093-231 figure 6 . minimum/maximum inl vs. external reference input voltage 8000 7000 6000 5000 4000 3000 2000 1000 0 number of occurrences code v dd = v drive = 3.3v v ref = 2.5v 8192 samples t a = 25c 290 7218 684 2028 2029 2030 12093-206 figure 7 . histogram of a dc input at code center 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 dnl (lsb) code v dd = 3.0v v ref = 2.5v f scl = 400khz t a = 25c positive dnl = +0.41 lsb negative dnl = ?0.41 lsb 0 512 1024 1536 2048 2560 3072 3584 4095 12093-208 figure 8 . differential nonlinearity vs. code 1.0 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 dnl (lsb) reference input voltage (v) min dnl (lsb) max dnl (lsb) v dd = 5.25v v ref = external f scl = 400khz t a = 25c 12093-234 figure 9 . minimum/maximum dnl vs. external reference input voltage 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 number of occurrences code v dd = v drive = 3.3v v ref = 2.5v 8192 samples t a = 25c 2042 2043 2044 2045 27 3762 4353 50 12093-209 figure 10 . histogram of a dc input at code transition
ad7091r- 5 data sheet rev. 0 | page 10 of 34 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 adc output spectrum (db) frequency (hz) 0 10000 8000 6000 4000 2000 v dd = v drive = 3.3v v ref = 2.5v external t a = 25c f in = 1khz f sample = 22.2ksps f scl = 400khz snr = 68.3db sinad = 68.2db thd = ?85.3db sfdr = ?88.2db 12093-207 figure 11 . 10 khz fft, v dd = 3.0 v, v ref = 2.5 v external 0 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 adc output spectrum (db) frequency (hz) 0 10000 8000 6000 4000 2000 v dd = v drive = 3.3v v ref = 2.5v internal f in = 1khz f sample = 22.2ksps f scl = 400khz snr = 68.4db sinad = 68.2db thd = ?83.3db sfdr = ?87.9db 12093-210 figure 12 . 10 khz fft, v dd = 3.0 v, v ref = 2.5 v internal 64 65 66 67 68 69 70 1 10 100 snr, sinad (db) input frequency (khz) 12093-108 v dd = 3.3v v ref = 2.5v signal amplitude = ?0.5db f scl = 400khz t a = 25c snr sinad figure 13 . snr , sinad vs. input frequency 66 snr, sinad (db) reference input voltage (v) 1.0 71 70 1.5 65 64 63 62 67 69 2.5 4.0 4.5 5.0 11.7 11.5 11.3 11.1 10.9 10.7 10.5 10.3 10.1 9.9 enob (bits) 2.0 3.0 3.5 68 enob sinad snr v dd = 3.0v v ref = external f scl = 400khz f in = 1khz signal amplitude = ?0.5db t a = 25c 12093-213 figure 14 . snr, sinad, and enob vs. reference input voltage ?90 ?88 ?86 ?84 ?82 ?80 ?78 ?76 ?74 ?72 ?70 1 10 100 thd (db) analog input frequency (khz) 12093-109 v dd = 3.3v v ref = 2.5v signal amplitude = ?0.5db f scl = 400khz t a = 25c figure 15 . thd vs. analog input frequency 70.0 69.5 69.0 68.5 68.0 67.5 67.0 66.5 66.0 snr (db) input level (db) v dd = 3.0v v ref = 2.5v f scl = 400khz f in = 1khz t a = 25c ?10 0 ?1 ?2 ?3 ?4 ?5 ?6 ?7 ?8 ?9 12093-215 figure 16 . snr vs. input level
data sheet ad7091r- 5 rev. 0 | page 11 of 34 thd, sfdr (db) reference input voltage (v) 1.0 ?75 1.5 ?95 ?93 ?91 ?89 ?87 ?85 ?83 ?81 ?79 ?77 2.5 4.0 4.5 5.0 2.0 3.0 3.5 sfdr thd v dd = 3.0v v ref = external f scl = 400khz f in = 1khz signal amplitude = ?0.5db t a = 25c 12093-216 figure 17 . thd , sfdr vs. reference input voltage ?81 ?85 ?90 ?55 thd (db) temperature (c) ?35 ?15 5 25 45 ?80 65 85 ?82 ?83 ?84 ?86 ?87 ?88 ?89 105 125 v dd = 5.0v f scl = 400khz f in = 1khz 12093-129 figure 18 . thd vs. temperature 68.6 ?55 snr (db) temperature (c) ?35 ?15 5 25 45 68.8 65 85 68.4 68.2 68.0 67.6 67.4 67.2 67.0 105 125 67.8 v dd = 3.0v v ref = 2.5v f scl = 400khz f in = 1khz 12093-122 figure 19 . snr vs. temperature operational i dd supply current (a) temperature (c) ?55 50 25 10 15 20 25 30 35 40 45 125 85 v dd = 3.0v v ref = internal 2.5v f scl = 400khz 2.70v 3.00v 5.25v 12093-220 figure 20 . operational i dd supply current vs. temperature for various v dd supply voltages 5 total power-down current ( a) temperature (c) ?40 8 25 4 3 2 1 0 85 125 6 7 3.3v 5.0v 5.25v 2.7v 12093-127 figure 21 . total power - down current vs. temperature for various suppl y voltages v ref (v) current load (a) 0 2.510 2.505 2.500 2.495 2.490 100 90 80 70 60 50 40 30 20 10 v dd = v drive = 3.0v ?55c ?40c +25c +85c +125c 12093-223 figure 22 . reference voltage output (v ref ) vs. current load for various temperatures
ad7091r- 5 data sheet rev. 0 | page 12 of 34 offset error (mv) temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 1.5 ?1.5 ?1.0 ?0.5 0 0.5 1.0 125 v dd = 3.0v v ref = 2.5v f scl = 400khz 12093-224 offset error ch 0 offset error ch 1 offset error ch 2 offset error ch 3 figure 23 . offset error vs. temperature ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?55 offset error match (mv) temperature (c) ?35 ?15 5 25 45 1.5 65 85 105 125 v dd = 3.0v v ref = 2.5v f scl = 400khz 12093-325 figure 24 . offset error match vs. temperature 75 80 85 90 95 100 1k psrr (db) ripple frequency (hz) 105 1m 100k 10k v dd = 3.0v v ref = 2.5v f scl = 400khz t a = 25c 12093-326 internal reference external reference figure 25 . psrr vs. ripple frequency gain error (% fs) temperature (c) ?55 ?35 ?15 5 25 45 65 85 105 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 125 v dd = 3.0v v ref = 2.5v f scl = 400khz 12093-227 gain error ch 0 gain error ch 1 gain error ch 2 gain error ch 3 figure 26 . gain error vs. temperature 0.08 0 ?0.10 ?55 gain error match (% fs) temperature (c) ?35 ?15 5 25 45 0.10 65 85 0.06 0.04 0.02 ?0.02 ?0.04 ?0.06 ?0.08 105 125 v dd = 3.0v v ref = 2.5v f scl = 400khz 12093-328 figure 27 . gain error match vs. temperature ?80 ?110 ?105 ?100 ?95 ?90 ?85 1 10 100 channel to channel isolation (db) input frequency (khz) v dd = 3.0v f sample = 22.22ksps f scl = 400khz t a = 25c 12093-229 figure 28 . channel to channel isolation vs. input frequency
data sheet ad7091r- 5 rev. 0 | page 13 of 34 ?85 ?105 ?103 ?101 ?99 ?97 ?95 ?93 ?91 ?89 ?87 ?55 ?35 ?15 5 25 45 65 85 105 125 channel to channel isolation (db) temperature (c) v dd = 3.0v f sample = 22.22ksps f scl = 400khz f in = 1khz 12093-230 figure 29 . channel to channel isolation vs. temperature ?85 ?80 ?75 ?70 ?65 ?60 ?55 ?50 10 100 1k 10k thd (db) source impedance () t a = 25c v dd = 3v f in = 10khz f scl = 400khz 12093-110 figure 30 . thd vs. source impedance 2.500 2.490 ?55 internal reference voltage (v) temperature (c) ?35 ?15 5 25 45 2.510 65 85 2.505 2.495 105 125 12093-135 figure 31 . internal reference voltage vs. temperature
ad7091r- 5 data sheet rev. 0 | page 14 of 34 terminology integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. for the ad7091r - 5 , the endpoints of the transfer function are zero scale, a point ? lsb below the first code transition, and full scale, a point ? lsb above the last code transition. differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error th e offset error is the deviation of the first code transition ( 00 000 to 00 001) from the ideal (such as g nd + 0.5 lsb). offset error match offset error match is the difference in offset error between any two input channels. gain error for the ad7091r - 5 , th e gain error is the deviation of the last code transition (111 110 to 111 111) from the ideal (such as v ref ? 1.5 lsb) after the offset error has been adjust ed out. gain error match gain error match is the difference in gain error between any two input channels . transient response time the tra ck - and - hold amplifier returns to track mode after the end of conversion. the track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 0.5 lsb, after the end of conversion . see the i 2 c int erface section for more details. signal -to - noise - and - distortion ratio (sinad) sinad is the measured ratio of the signal - to - n oise - and - distortion at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza tion process ; the more levels, the smaller the quantization noise. the theoretical sinad for an ideal n - bit converter with a sine wave input is given by signal - to - (noise + distortion ) = ( 6.02 n + 1.76 ) ( db ) thus, for a 12 - bit converter, the sinad ratio is 74 db. channel to channel isolation channel to channel isolation is a measure of the level of crosstalk between the selected channel and all the other channels. it is measured by applying a full - scale, 10 khz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel that has a dc sign al applied to it. figure 28 shows the worst case across all channels for the ad7091r - 5 . total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental . for the ad7091r - 5 , it is defined as ( ) 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 db + + + + = v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum; however, for adcs where the harmonics are buried in th e noise floor, it is a noise peak.
data sheet ad7091r-5 rev. 0 | page 15 of 34 theory of operation circuit information the ad7091r-5 is a 12-bit, ultralow power single-supply adc. the device operates from a 2.7 v to 5.25 v supply. the ad7091r-5 can function in both standard and fast i 2 c operating modes. the ad7091r-5 provides a 4:1 multiplexer and an on-chip, track-and-hold amplifier, and is housed in either a 20-lead lfcsp or 20-lead tssop package. these packages offer con- siderable space-saving advantages over alternative solutions. the serial clock input accesses data from the device. an internally generated clock is implemented to control the successive approximation adc. the reference voltage for the ad7091r-5 is provided externally or is generated internally by an accurate on-chip reference source. the analog input range for the ad7091r-5 is 0 v to v ref . the ad7091r-5 also features a power-down option to save power between conversions. the power-down feature is accessed through the standard serial interface as described in the modes of operation section. converter operation the ad7091r-5 is a successive approximation adc based on a charge redistribution digital-to-analog converter (dac). figure 32 and figure 33 show simplified schematics of the adc. figure 32 shows the adc during its acquisition phase. when switch 2 (sw2) is closed and switch 1 (sw1) is in position a, the comparator is held in a balanced condition, and the sampling capacitor acquires the signal on adc in . control logic comparator sw2 sampling capacitor acquisition phase sw1 a b gnd charge dac redistribution adc in v dd /2 12093-015 figure 32. adc acquisition phase control logic comparator sw2 sampling capacitor conversion phase sw1 a b gnd charge dac redistribution a dc in v dd /2 12093-016 figure 33. adc conversion phase when the adc starts a conversion, sw2 opens and sw1 moves to position b, causing the comparator to become unbalanced (see figure 33). using the control logic, the charge redistribution dac adds and subtracts fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. when the sar decisions are made, the comparator inputs are rebalanced. from these sar decisions, the control logic generates the adc output code. adc transfer function the output coding of the ad7091r-5 is straight binary. the designed code transitions occur midway between successive integer lsb values, such as ? lsb and 1? lsb. the lsb size for the ad7091r-5 is v ref /4096. the ideal transfer characteristic for the ad7091r-5 is shown in figure 34. 000...000 0v adc code analog input 111...111 000...001 000...010 111...110 111...000 011...111 1lsb +v ref ? 1lsb 1lsb = v ref /4096 12093-017 figure 34. transfer characteristic reference the ad7091r-5 can operate with either the internal 2.5 v on-chip reference or an externally applied reference. the logic state of the p_down lsb bit in the configuration register determines whether the internal reference is used. the internal reference is selected for the adcs when the p_down lsb bit is set to 1. when the p_down lsb bit is set to 0, supply an external reference in the range of 2.5 v to v dd through the ref in / ref out pin. at power-up, the internal reference disables by default. the internal reference circuitry consists of a 2.5 v band gap reference and a reference buffer. when operating the ad7091r-5 in internal reference mode, the 2.5 v internal reference is available at the ref in /ref out pin, which is typically decoupled to gnd using a 2.2 f capacitor. it is recommended to buffer the internal reference before applying it elsewhere in the system. the reference buffer requires 50 ms to power up and charge the 2.2 f decoupling capacitor.
ad7091r-5 data sheet rev. 0 | page 16 of 34 power supply the ad7091r-5 uses two power supply pins: a core supply (v dd ) and a digital input/output interface supply (v drive ). v drive allows direct interfacing with any logic between 1.8 v and 5.25 v. to reduce the number of supplies needed, v drive and v dd can be tied together depending upon the logic levels of the system. the ad7091r-5 is independent of power supply sequencing between v drive and v dd . additionally, the ad7091r-5 is insensitive to power supply variations over a wide frequency range, as shown in figure 25. the ad7091r-5 powers down automatically at the end of each conversion phase; therefore, the power scales linearly with the sampling rate. the automatic power-down feature makes the ad7091r-5 device ideal for low sampling rates (of even a few hertz) and battery-powered applications. table 6. recommended power management devices 1 product description adp7102 20 v, 300 ma, low noise, cmos ldo adm7160 ultralow noise, 200 ma linear regulator adp162 ultralow quiescent current, cmos linear regulator 1 for the latest recommended power management devices, see the ad7091r-5 product page. device reset upon power-up, a reset pulse of at least 10 ns in width must be provided on the reset pin to ensure proper initialization of the device. failure to apply the reset pulse may result in a device malfunction. see figure 35 for reset pulse timing relative to power supply establishment. at any time, the reset pin can reset the device and the contents of all internal registers, including the command register, to their default state. to activate the reset operation, bring the reset pin low for a minimum of 10 ns while it is asynchronous to the scl signal. it is imperative that the reset pin be held at a stable logic level at all times to ensure normal operation. 12093-141 reset v dd v drive t resetpw t reset_delay figure 35. reset pin power up timing analog input figure 36 shows an equivalent circuit of the analog input structure of the ad7091r-5 . the two diodes, d1 and d2, provide esd protection for the analog input. ensure that the analog input signal never exceeds the supply rails by more than 300 mv because this causes these diodes to become forward-biased and start conducting current into the substrate. these diodes can conduct a maximum of 10 ma without causing irreversible damage to the device. d1 d2 r1 500 ? c2 3.6pf c1 400ff conversion phase switch open track phase switch closed d3 v in x v dd ref in / ref out 12093-019 figure 36. equivalent analog input circuit the c1 capacitor in figure 36 is typically approximately 400 ff and can primarily be attributed to pin capacitance. the r1 resistor is a lumped component made up of the on resistance of a switch. this resistor is typically approximately 500 . the c2 capacitor is the adc sampling capacitor and typically has a capacitance of 3.6 pf. in applications where harmonic distortion and snr are critical, drive the analog inputs from low impedance sources. large source impedances significantly affect the ac performance of the adc, which can necessitate using input buffer amplifiers, as shown in figure 37. the choice of the op amp is a function of the particular application. when no amplifiers are driving the analog input, limit the source impedance to low values. the maximum source impedance depends on the amount of thd that can be tolerated. the thd increases as the source impedance increases and performance degrades. use an external filter on the analog input signal paths to the ad7091r-5 v in x pins to achieve the specified performance. this filter can be a one-pole, low-pass rc filter or similar. connect the mux out pin directly to the adc in pin. insert a buffer amplifier in the path, if desired. when sequencing channels, do not place a filter between mux out and the input to any buffer because doing so leads to crosstalk. if a buffer is not implemented, do not place a filter between mux out and adc in when sequencing channels because doing so leads to crosstalk.
data sheet ad7091r- 5 rev. 0 | page 17 of 34 driver amplifier cho ice although the ad7091r - 5 is easy to drive, a driver amplifie r must meet the following requirements: ? keep t he noise generated by the driver amplifier as low as possible to preserve the snr and transition noise performance of the ad7091r - 5 . the noise from the driver is filtered by the one - pole, low - pass filter of the ad7091r - 5 analog input circuit , made by r1 and c2 , or by the external filter, if one is used. because the typical noise of the ad7091r - 5 is 350 v rms, t he snr degr adation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 350 350 log 20 n 3db loss ne f snr where: f ?3db is the input bandwidth, in megahertz, of the ad7091r - 5 (1 .5 mhz) , or the cutoff fre quency of the input filter, if one is used. n is the noise gain of the amplifier ( for ex ample, gain = 1 in a buffer ed configuration ; see figure 37). e n is the equivalent input noise voltage of the op amp, in nv/hz. ? for ac applications, t he driver must have a thd performance that is commensurate with the ad7091r - 5 . ? if a buffer is placed between mux out and adc in , the driver amplifier and the ad7091r - 5 analog input circuit must settle for a full - scale step onto the capacitor array at a 12 - bit level (0.0244%, 244 ppm). in an amplifier data sheet, settling at 0.1% to 0.01% is more co mmonly specified and may differ significantly from the settling time at a 12 - bit level. be sure to verify the amplifier settling time before driver selection. table 7 . recommended driver amplifiers product description 1 ada4805 - 1 low noise, low power , wide bandwidth amplifier ad8031 low voltage, low power, single channel amplifier ad8032 low voltage, low power, dual channel amplifier ad8615 low frequency, low voltage amplifier 1 f or the latest recommended adc driver products , see the ad7091r - 5 product page . typical connection d iagram figure 37 and figure 38 sho w typical connection diagram s for the ad7091r - 5 . connect a positive power supply in the 2.7 v to 5.25 v range to the v dd pin. t he t ypical value s for the v dd decoupling capacitors are 100 nf and 10 f. place these capacitors as close as possible to the device pins. take care to decouple the ref in /ref out pin to achieve specified performance. the typical value for the r ef in /ref out capacitor is 2.2 f, which provides an analog inpu t range of 0 v to v ref . the typical value for the regulator bypass (regcap) decoupling capacitor is 1 f. the voltage applied to the v drive input controls the voltage of the serial interface; th erefore, connect this pin to the supply voltage of the microprocessor. set v drive in the 1.8 v to 5.25 v range. t he t ypical values for the v drive decoupling capacitor s are 100 nf and 10 f. t h e 1 6 - bit conversion result ( 3 address bits, 1 alert bit, and 12 data bits) is output in 2 bytes with the most significant byte (msbs) presented first. when an externally applied reference is required, disable the internal reference using the configuration register. choose an external ly applied reference voltage in the range of 1.0 v to v dd and connect it to the ref in /ref out pin. for applications where power consumption is a concern, use the power - down mode of the adc to improve power performance. see the modes of operation section for additional details.
ad7091r-5 data sheet rev. 0 | page 18 of 34 ad7091r-5 scl sda microcontroller/ microprocessor/ dsp as 1 v in 0 gnd v dd 10f 100nf 10f 100nf regcap 1f as 0 2.2f a nalo g input 47k ? v drive v drive ref in / ref out a nalo g input convst/gpo 1 alert/busy/gpo 0 v in 3 optional buffer adc in mux out 560pf 33 ? 12093-018 figure 37. typical connection diagram with optional buffer ad7091r-5 scl sda microcontroller/ microprocessor/ dsp as 1 v in 0 gnd v dd 10f 100nf 10f 100nf regcap 1f as 0 2.2f a nalo g input 33 ? 560pf 47k ? v drive v drive ref in / ref out a nalo g input 33 ? 560pf convst/gpo 1 alert/busy/gpo 0 v in 3 adc in mux out 12093-140 figure 38. typical connection diagram without optional buffer
data sheet ad7091r- 5 rev. 0 | page 19 of 34 i 2 c registers the ad7091r - 5 has several user - programmable registers. table 9 contains the complete list of registers. the registers are either read/write (r/w) or read only (r). data can be written to or read back from the read/write registers. read only registers can only be read. any write t o a read only register or unimplemented register address is considered no operation (nop) command , which is an i 2 c command that the ad7091r - 5 ignore s . after a write to a read only register, the output on the subsequent i 2 c frame is all zeros provided that there was no conversion before the next i 2 c frame. similarly, any re ad of an unimplemented register outputs zeros. addressing registers a serial transfer on the ad7091r - 5 consists of nine scl cycles. data is sent over the serial bus in groups of nine bits eight bits of data from the transmitter followed by an acknowledge bit from th e receiver. data transitions on the sda line must occur during th e low period of the clock signal and remain stabl e during the high period. the receiver pull s the sda line low during the acknowledge bit to signal that the preceding byte has been received c orrectly. if this is not the case, cancel the transaction. the first byte that the master sends must consist of a 7 - bit slave address, followed by a data direction bit. each device on the bus has a unique slave address; therefore, the first byte sets up communication with a single slave device for the duration of the transaction. the transaction can be used either to write to a slave device (data direction bit = 0) or to read data from it (data direction bit = 1 ). in the case of a read transaction, it is often necessary to first write to the slave device (in a separate write transaction) to tell it from which register to read. reading and writing cannot be combined in one transaction. when the transaction is complete, the master can maintain control of the bus, initiating a new transaction by generating another start bit (high to low transition on sda while scl is high). this is known as a repeated start. alternatively, the bus can be relinquished by releasing the scl line followed by the sda line. this low to high transition on sda while scl is high is known as a stop bit (p), and it leaves the i 2 c bus in its idle state (no current is consumed by the bus). slave address the first byte that the user writes to the device is the slave address byte. the ad7091r - 5 has a 7 - bit slave address. on the ad7091r - 5 , the three msbs of the 7 - bit slave address are fixed to 3b010. the four lsbs are set by the user via external pins. two address select pins are on each device, and high, low , or no connect can be detected on each pin , giving nine combination s. table 8 shows the four lsbs of the slave address for the ad7091r - 5 for different configurations of the address select pins. table 8 . slave address es as 1 1 as 0 1 a3 a2 a1 a0 v dd v dd 0 0 0 0 v dd nc 0 0 1 0 v dd gnd 0 0 1 1 nc v dd 1 0 0 0 nc nc 1 0 1 0 nc gnd 1 0 1 1 gnd v dd 1 1 0 0 gnd nc 1 1 1 0 gnd gnd 1 1 1 1 1 nc means leave the as x pins floating , v dd means pulled high, and gnd means pulled low . i 2 c register access t able 9 . register description s address register name default access 0x00 conversion result 0x0000 r 0x01 channel 0x0000 r/w 0x02 configuration 0x00c0 r/w 0x03 alert i ndication 0x0000 r 0x04 channel 0 low limit 0x0000 r/w 0x05 channel 0 high limit 0x01ff r/w 0x06 channel 0 hysteresis 0x01ff r/w 0x07 channel 1 low limit 0x0000 r/w 0x08 channel 1 high limit 0x01ff r/w 0x09 channel 1 hysteresis 0x01ff r/w 0x0a channel 2 low limit 0x0000 r/w 0x0b channel 2 high limit 0x01ff r/w 0x0c channel 2 hysteresis 0x01ff r/w 0x0d channel 3 low limit 0x0000 r/w 0x0e channel 3 high limit 0x01ff r/w 0x0f channel 3 hysteresis 0x01ff r/w
ad7091r-5 data sheet rev. 0 | page 20 of 34 conversion result register the conversion result register is a 16-bit, read only register th at stores the results from the most recent adc conversion in s traight binary format. the channel id of the converted channel and the alert status are also included in this register. re s e r v e d 12 -b it conve rsion result 2-bit channel id alert flag 1: alert has occured. 0: no alert. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [15] rsv (r) [ 11:0 ] co nv_result ( r) [14:13] ch_id (r) [12] alert (r) table 10. conversion result bit map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 rsv ch_id alert conv_result table 11. bit descriptions for the conversion result register bit(s) name description reset access 15 rsv reserved 0x0 r [14:13] ch_id 2-bit channel id of the channel converted 0x0 r b14 b13 analog input channel 0 0 channel 0 0 1 channel 1 1 0 channel 2 1 1 channel 3 12 alert alert flag 0x0 r 0: no alert occurred 1: alert has occurred [11:0] conv_result 12-bit conversion result 0x000 r
data sheet ad7091r-5 rev. 0 | page 21 of 34 channel register the channel register on the ad7091r-5 is an 8-bit, read/write register. each of the four analog input channels has one corresponding bit in the channel register. to select a channel for inclusion in the channel conversion sequence, set the corresponding channel bit t o 1 in the channel register. there is a latency of one conversion before the channel conversion sequence is updated. if the channel regist er is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value. rese rved convert on channel 0 1: enable channel 0 . 0: disable channel 0. co nvert on channe l 3 1: enable channel 3. 0 : disab le channel 3. convert on channel 1 1: enable channel 1. 0: disable channel 1. co nvert on channe l 2 1: enable channel 2. 0 : disab le channel 2. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7:4] rsv (r) [0] ch0 (r/w) [3] ch3 (r/w) [1] ch1 (r/w) [2] ch2 (r/w) table 12. channel bit map msb lsb b7 b6 b5 b4 b3 b2 b1 b0 rsv ch3 ch2 ch1 ch0 table 13. bit descriptions for the channel register bit(s) name description reset access [7:4] rsv reserved 0x00 r 3 ch3 convert on channel 3 0x0 r/w 0: disable channel 3 1: enable channel 3 2 ch2 convert on channel 2 0x0 r/w 0: disable channel 2 1: enable channel 2 1 ch1 convert on channel 1 0x0 r/w 0: disable channel 1 1: enable channel 1 0 ch0 convert on channel 0 0x0 r/w 0: disable channel 0 1: enable channel 0
ad7091r-5 data sheet rev. 0 | page 22 of 34 configuration register the configuration register is a 16-bit, read/write register that sets the operating modes of the ad7091r-5 . drive type of alert/busy/gpo0 pin 1: typ e . alert/busy/gpo0 pin is of cmos drive 0: drive type. alert/busy/gpo0 pin is of open-drain po w e r d o w n m o d e 11: mode 3. 10: mode 2. 01: mode 1. 00: mode 0. value at gpo 2 1: drive '1' o n gpo2 p in. 0 : drive '0 ' o n gpo2 p in. value at gpo 1 1: drive '1' o n gpo1 p in. 0: drive '0' on gpo1 pin. re s e r v e d polarity of alert/busy/gpo0 pin (if alert_en is 1) o r v alue at gpo 0 1: is 1) o r gpo 0 = 1. active high alert po larity(if alert_en 0: is 1) o r gpo 0 = 0 . active low alert po larity(if alert_en re s e r v e d en a b le alert o r gpo 0 0: a gpo. alert/busy/gpo 0 p in w ill b e us e d as 1: status. alert/busy/gpo0 p in is use d fo r alert/bus y enab le glitc h filte r o n sda/scl 1: by p as s the glitc h-filte r. 0: line s . enab le '50 ns ' glitc h-filte ring o n sda/scl alert/busy/gpo0 p in ind icate s if the p art is b usy co nve rting 1: this w ill alw ay s b e re ad -b ac k as 0 . s ta tu s p r o v id e d alert_en is 1 . els e , alert/busy/gpo0 pin is used for busy 0: busy status. alert/busy/gpo0 p in is no t use d fo r co m m and mo d e 1: mode(if auto = 1) command mode (if auto = 0) or sample 0: mode(if auto = 1) sam p le m o d e (if auto = 0 ) o r auto cycle timer value for autocycle mode 11: 8 00 us. 10: 4 00 us. 01: 200 us. 00: 100 us. so ftw are re se t b it 1: activate so ft-re se t. 0: soft-reset not active. autocycle mode 1: mode(if cmd = 1) auto-cycle mode (if cmd = 0) or sample 0: mode(if cmd = 1) sample mode (if cmd = 0) or command 0 0 1 0 2 0 3 0 4 0 5 0 6 1 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15 0 [ 1 5 ] alert_d rive_type ( r/w ) [ 1:0 ] p_d o w n ( r/w ) [14] gpo2 (r/w) [2] gpo1 (r/w) [13] rsv (r) [3] alert_po l_o r_gpo 0 (r/w ) [12] rsv (r) [4] alert_en_or_gpo0 (r/w) [11] fltr (r/w ) [5] busy (r/w) [10] cmd (r/w) [7 :6 ] cycle _tim e r (r/w ) [9 ] srst (r/w ) [8] auto (r/w) table 14. configuration bit map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 alert_ drive_ type gpo2 rsv rsv fltr cmd srst auto cycle_ timer busy alert_ en_or_ gpo0 alert_ pol_or_ gpo0 gpo1 p_down table 15. bit descriptions for the configuration register 1 bit(s) name description reset access 15 alert_drive_type drive the type of the alert/busy/gpo 0 pin. 0x0 rw 0: the alert/busy/gpo 0 pin is open-drain drive type. 1: the alert/busy/gpo 0 pin is cmos drive type. 14 gpo2 value at gpo 2 . 0x0 rw 0: drive 0 on gpo 2 pin. 1: drive 1 on gpo 2 pin. 13 rsv reserved. 0x00 r 12 rsv reserved. 0x00 r
data sheet ad7091r-5 rev. 0 | page 23 of 34 bit(s) name description reset access 11 fltr enable the glitch filter on sda/scl. 0x0 rw 0: enable 50 ns glitch filtering on the sda/scl lines. 1: bypass the glitch filter. 10 cmd command mode. 0x0 rw 0: sample mode (if auto = 0) or autocycle mode (if auto = 1). 1: command mode (if auto = 0) or sample mode (if auto = 1). 9 srst software reset bit. setting this bit resets the internal digital control logic, the conversion result and alert indication registers, but not the other memory-mapped registers. this bit is automatically cleared in the next clock cycle. 0x0 rwac 0: soft reset not active. 1: activate soft reset. 8 auto autocycle mode. 0x0 rw 0: sample mode (if cmd = 0) or command mode (if cmd = 1). 1: autocycle mode (if cmd = 0) or sample mode (if cmd = 1). [7:6] cycle_timer timer value for autocycle mode. 0x3 rw 00: 100 s. 01: 200 s. 10: 400 s. 11: 800 s. 5 busy alert/busy/gpo 0 pin indicates if the device is busy converting. 0x0 rw 0: the alert/busy/gpo 0 pin is not used for the busy status. 1: the alert/busy/gpo 0 pin is used for the busy status provided alert_en_or_gpo0 is 1. otherwise, this bit is always read back as 0. 4 alert_en_or_gpo0 enable the alert/busy/gpo 0 pin or gpo0. 0x0 rw 1: the alert/busy/gpo 0 pin is used for the alert/busy status. 0: the alert/busy/gpo 0 pin is used as a gpo. 3 alert_pol_or_gpo0 polarity of the alert/busy/gpo 0 pin (if alert_en_or_gpo0 is 1) or value at gpo0. 0x0 rw 0: active low alert/busy/gpo 0 polarity (if alert_en_or_gpo0 is 1) or gpo0 = 0. 1: active high alert/busy/gpo 0 polarity (if alert_en_or_gpo0 is 1) or gpo0 = 1. 2 gpo1 value at gpo 1 . 0x0 rw 0: drive 0 on the convst /gpo 1 pin. 1: drive 1 on the convst /gpo 1 pin. [1:0] p_down power-down modes. 0x0 r/w setting mode sleep mode/bias generator internal reference 00 mode 0 off off 01 mode 1 off on 10 mode 2 on off 11 mode 3 on on 1 the ad7091r-5 supports the i 2 c standard glitch filter, but does not support clock stretching or general call addressing.
ad7091r-5 data sheet rev. 0 | page 24 of 34 alert indication register the 8-bit alert indication register is a read only register that provides information on an alert event. if a conversion result activates the alert/busy/gpo 0 pin, as described in the channel x low limit register se ction and the channel x high limit register section, read the alert register to determine the source of the alert. the register contains two status bits per channel, one corresponding t o the high limit, and the other to the low limit. the bit with a status equal to 1 shows where the violation occurred, that is, on which c hannel, and whether the violation occurred on the upper or lower limit. if a second alert event occurs on another channel between receiving the first alert and interrogating the alert register, the corresponding bit for that alert event is also set. the contents of the alert indication register are reset by reading it. when the ad7091r-5 uses the i 2 c interface to read the alert indication register, the register is reset at the fourth scl clock of the byte. by this time, the data from the register has moved to the i 2 c shift register. the alert bits for any unimplemented channels always return zeros. low alert channel 3 1: low alert occurred on channel 3 . 0: no alert on channel 3 . hig h alert channel 0 1: high alert occurred on channel 0 . 0: no alert o n channel 0. high alert channel 3 1: high ale rt o ccurre d o n channel 3. 0: no alert on channel 3 . lo w alert channel 0 1: low ale rt occurre d o n channel 0. 0: no alert o n channel 0. low alert channel 2 1: low alert occurred on channel 2 . 0: no alert on channel 2 . hig h alert channel 1 1: high alert occurred on channel 1. 0: no alert o n channel 1. high alert channel 2 1: high ale rt o ccurre d o n channel 2. 0: no alert on channel 2 . lo w alert channel 1 1: low ale rt occurre d o n channel 1. 0: no alert o n channel 1. 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 [7] lo_3 (r) [0] hi_0 (r) [6] hi_3 (r) [1] lo_0 (r) [5] lo_2 (r) [2] hi_1 (r) [4] hi_2 (r) [3] lo_1 (r) table 16. alert indication bit map table 17. bit descriptions for the alert indication register bit(s) bit name description reset access 7 lo_3 channel 3 low alert status 0x0 r 0: no alert on channel 3 1: low alert occurred on channel 3 6 hi_3 channel 3 high alert status 0x0 r 0: no alert on channel 3 1: high alert occurred on channel 3 5 lo_2 channel 2 low alert status 0x0 r 0: no alert on channel 2 1: low alert occurred on channel 2 4 hi_2 channel 2 high alert status 0x0 r 0: no alert on channel 2 1: high alert occurred on channel 2 3 lo_1 channel 1 low alert status 0x0 r 0: no alert on channel 1 1: low alert occurred on channel 1 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 lo_3 hi_3 lo_2 hi_2 lo_1 hi_1 lo_0 hi_0
data sheet ad7091r-5 rev. 0 | page 25 of 34 bit(s) bit name description reset access 2 hi_1 channel 1 high alert status 0x0 r 0: no alert on channel 1 1: high alert occurred on channel 1 1 lo_0 channel 0 low alert status 0x0 r 0: no alert on channel 0 1: low alert occurred on channel 0 0 hi_0 channel 0 high alert status 0x0 r 0: no alert on channel 0 1: high alert occurred on channel 0
ad7091r-5 data sheet rev. 0 | page 26 of 34 channel x low limit register each analog input channel of the ad7091r-5 has its own low limit register. the low limit registers are 16-bit read/write registers. see table 9 for the register addresses. the low limit registers store the lower limit of the conversion value that activates the alert output. of the 16 bits, only the twelve least significant bits (lsbs) are used, bit b11 to bit b0. bit b15 to bit b12 are not used. channel x high limit register each analog input channel of the ad7091r-5 has its own high limit register. the high limit registers are 16-bit read/write registers. see table 9 for the register addresses. the high limit registers store the upper limit of the conversion value that activates the alert output. of the 16 bits, only the twelve least significant bits (lsbs) are used, bit b11 to bit b0. bit b15 to bit b12 are not used. channel x hysteresis register each analog input channel of the ad7091r-5 has its own hysteresis register, which are 16-bit read/write registers. see table 9 for the register addresses. the hysteresis register stores the hysteresis value (n) when using the limit registers. the hysteresis value determines the reset point for the alert/ busy/gpo 0 pin if a violation of the limits has occurred. of the 16 bits, only the twelve least significant bits (lsbs) are used, bit b11 to bit b0. bit b15 to bit b12 are not used. table 18. channel x low limit bit map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 rsv chx low limit table 19. bit descriptions for channel x low limit register bits bit name description reset access [15:12] rsv reserved 0x00 r [11:0] chx low limit low limit value for channel x 0x000 r/w table 20. channel x high limit bit map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 rsv chx high limit table 21. bit descriptions for channel x high limit register bits bit name description reset access [15:12] rsv 0x00 r [11:0] chx high limit high limit value for channel x 0xfff r/w table 22. channel x hysteresis bit map msb lsb b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 rsv chx hysterisis table 23. bit descriptions for th e channel x hysteresis register bits bit name description reset access [15:12] rsv 0x00 r [11:0] chx hysterisis hysteresis value for channel x 0xfff r/w
data sheet ad7091r-5 rev. 0 | page 27 of 34 i 2 c interface control of the ad7091r-5 is carried out via the i 2 c-compatible serial bus. the ad7091r-5 is connected to this bus as a slave device under the control of a master device such as the processor. serial bus address byte the first byte that the user writes to the device is the slave address byte. similar to all i 2 c-compatible devices, the ad7091r-5 has a 7-bit serial address. the three msbs of this address are set to 010. the four lsbs are user programmable by the three-state input pins, as 0 and as 1 , as shown in table 24. in table 24, high means tie the pin to v drive , low means tie the pin to gnd, and nc refers to a pin left floating. note that in nc cases, the stray capacitance on the pin must be less than 30 pf to allow correct detection of the floating state; therefore, any printed circuit board trace must be kept as short as possible. table 24. slave address control using three-state input pins as 1 as 0 slave address (a6 to a0) binary hex high high 010 0000 0x20 high nc 010 0010 0x22 high low 010 0011 0x23 nc h 010 1000 0x28 nc nc 010 1010 0x2a nc low 010 1011 0x2b low high 010 1100 0x2c low nc 010 1110 0x2e low low 010 1111 0x2f general i 2 c timing figure 39 shows the timing diagram for general read and write operations using an i 2 c compliant interface. when no device is driving the bus, both scl and sda are high. this is known as the idle state. when the bus is idle, the master initiates a data transfer by establishing a start condition, defined as a high to low transition on the serial data line (sda) while the serial clock line (scl) remains high. this indicates that a data stream follows. the master device must generate the clock. data is sent over the serial bus in groups of nine bitseight bits of data from the transmitter are followed by an acknowledge bit (ack) from the receiver. data transitions on the sda line must occur during the low period of the clock signal and remain stable during the high period. the receiver must pull the sda line low during the acknowledge bit to signal that the preceding byte has been received correctly. if this is not the case, cancel the transaction. the first byte that the master sends must consist of a 7-bit slave address, followed by a data direction bit. each device on the bus has a unique slave address; therefore, the first byte sets up communication with a single slave device for the duration of the transaction. the transaction can be used either to write to a slave device (data direction bit = 0) or to read data from it (data direction bit = 1). in the case of a read transaction, it is often necessary first to write to the slave device (in a separate write transaction) to tell it from which register to read. reading and writing cannot be combined in one transaction. when the transaction is complete, the master can maintain control of the bus, initiating a new transaction by generating another start bit (high to low transition on sda while scl is high). this is known as a repeated start (sr). alternatively, the bus can be relinquished by releasing the scl line followed by the sda line. this low to high transition on sda while scl is high is known as a stop bit (p), and it leaves the i 2 c bus in its idle state (no current is consumed by the bus). the example in figure 39 shows a simple write transaction with an ad7091r-5 as the slave device. in this example, the ad7091r-5 register pointer is being set up for a future read transaction. p7 p6 p5 p4 p3 p2 p1 p0 start cond by master ack. by ad7091r-5 slave address byte ack. by ad7091r-5 scl s d a register address stop by master user programmable 4 lsbs r/w a6 a5 a4 a3 a2 a1 a0 12093-040 figure 39. general i 2 c timing
ad7091r-5 data sheet rev. 0 | page 28 of 34 writing to the ad7091r-5 writing two bytes of data to a 16-bit register with the exception of the channel register, all registers on the ad7091r-5 are 16-bit registers; therefore, two bytes of data are required to write a value to any one of these registers. writing two bytes of data to a register consists of the following sequence (see figure 40): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends a register address. the slave asserts an acknowledge on sda. 5. the master sends the first data byte (most significant). 6. the slave asserts an acknowledge on sda. 7. the master sends the second data byte (least significant). 8. the slave asserts an acknowledge on sda. 9. the master asserts a stop condition on sda to end the transaction. writing to multiple registers writing to multiple address registers consists of the following steps (see figure 41): 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device ( ad7091r-5 ) asserts an acknowledge on sda. 4. the master sends a register address, for example, the configuration register address. 5. the slave asserts an acknowledge on sda. 6. the master sends the first data byte. 7. the slave asserts an acknowledge on sda. 8. the master sends the second data byte. 9. the slave asserts an acknowledge on sda. 10. the master sends a second register address, for example, the channel 0 high limit register. 11. the slave asserts an acknowledge on sda. 12. the master sends the first data byte. 13. the slave asserts an acknowledge on sda. 14. the master sends the second data byte. 15. the slave asserts an acknowledge on sda. 16. the master asserts a stop condition on sda to end the transaction. s slave address 0 sa reg pointer sa data[15:8] sa p data[7:0] sa from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge 12093-059 figure 40. writing two bytes of data to a 16-bit register s ... ... 0 sa sa slave address point to config reg (0x02) p sa sa sa data[7:0] data[15:8] point to ch0 high limit (0x05) data[15:8] sa sa data[7:0] from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge 12093-060 figure 41. writing to multiple registers
data sheet ad7091r- 5 rev. 0 | page 29 of 34 reading data f rom the ad7091r- 5 reading two bytes of data from a 16 - bit register reading the contents from any of the 16 - bit registers is a 2 - byte read operation. in this protocol, the first part of the transaction writes to the register pointer. when the register address has been set up, any number of reads can be performed from that particular register without writ ing to the address pointer register again. when the required number of reads is complete, the master must not acknowledge the final byte. this tells the slave to stop transmitting, allowing a stop condition to be asserted by the master. further reads from this register can be performed in a future transaction without rewriting to the register pointer. if a read from a different address is required, the relevant register address must be written to the address pointer register and, again, any number of reads from this register can then be performed. in the following example, the master device reads three lots of 2 - byte data from a slave device , but as many lots consisting of two bytes can be read as required. this protocol assu mes that the particular register address has been set up by a single - byte write operation to the address pointer register. reading two bytes of data from a 16 - bit register consists of the following sequence (see figure 42): 1. the master device asserts a start condition on sda. 2. the master sends the 7 - bit slave address followed by the read bit (high). 3. the address ed slave device asserts an acknowledge on sda. 4. the m aster receives the data byte. 5. the master asserts an acknowledge on sda. 6. the master receives the second data byte. 7. the master asserts an acknowledge on sda. 8. the master receives the data byte. 9. the master asserts an acknowledge on sda. 10. the master receives t he second data byte. 11. the master asserts an acknowledge on sda. 12. the master receives the data byte. 13. the master asserts an acknowledge on sda. 14. the master receives the second data byte. 15. the master asserts a not acknowledge on sda to notify the slave that th e data transfer is complete. 16. the master asserts a stop condition on sda to end the transaction. s a p .. . .. . 1 a a a a a a slave address data[7:0] data[7:0] data[7:0] data[15:8] data[15:8] data[15:8] from master to slave from slave to master s = start condition sr = repeated start p = stop condition a = acknowledge a = not acknowledge 12093-061 figure 42 . reading three lots of two bytes of data from the conversion result register (conversion re gister p ointer a lready s et)
ad7091r- 5 data sheet rev. 0 | page 30 of 34 modes of operation there are three methods of initiating a conversion on the ad7091r - 5 with the i 2 c interface : s ample mode using the convst /gpo 1 pin , c ommand mode , and a utocycle mode. in the convst /gpo 1 pin mode, conversions are done on demand. whenever the convst /gpo 1 pin is toggled, an adc conversion happens. in command mode, the read of the conversion result register starts the conversion. in autocycle mode, conversions occur on the selected channels in the background periodically. this mode monitor s whether signals cross certain threshold levels, the absolute value being relatively unimportant. sample mode at power - up, the device wakes up in sample mode and selects c hannel 0 for conversion. sample mode can be selected subse - quently by writing a value of 0 to both the cmd and auto bits of the configuration register or by writing a value of 1 to both the cmd and auto b its. in sample mode, conversion s are controlled by toggling the active low conv st /gpo 1 pin. to perform conver sion on a channel other than channel 0 or on a sequence of channels, before initiating any conversion, write to the channel register to select the channels for conversion. on each convst pulse, the next channel in the selected sequence is converted starting from t he lowest numbered channel selected (0, 1 7). a high to low transition on the convst /gpo 1 pin put s the track - and - hold circuit into hold mode and samples the analog input. the conversion is initiated and requires approximately 550 ns to complete. when the conversion process is finished, the track - and - hold circuit goes back into track. to read back data stored in the conversion result regis ter, first wait until the conversion is finished. if the address pointer is pointing to the conversion result register , the conversion data can be read using the protocol described in figure 42. otherwise , the address pointer must be set to point at the conversion result register before conversion data can be read . when the conversion result read is completed, the user may pull the convst pin low again to start another conversion. do not toggle t he convst pin when activity is occurring on the i 2 c bus. command mode in command mode, the ad7091r - 5 converts on demand on either a single channel or a sequence of channels. this mode of operation allows a conversion to be selected automatically any time a write operation occurs to the command register. in command mode, the ad7091r - 5 converts the next programmed chann el when the conversion result register is read. to enter this mode, the required combination of channels is written into the channel register . select c ommand mode operation b y writing cmd = 1 and auto = 0 in the configuration register . following the write operation, the ad7091r - 5 must be addressed again to indicate that a read operation is required from the conversion result re gister . the conversion start s on the first positive edge of scl after the ack for the previous byte is sent to avoid starting a conversion during the ack cycle. this does not create an issue with the exact time that the conversion data must be sent on the i 2 c bus because the first three bits sent on the i 2 c bus correspond to the channel for which the conversion data belongs. after the conversion is completed, the adc power s down. the next conversion in the sequence starts after a subsequent read from the conversion result register is initiated. the device cycles through the selected channels from the lowest selected channel number in the sequence t o the next until all channels in the sequence are converted. after all channels in the sequence are converted, the sequence roll s back to the lowest numbered channel enabled so that the sequence can be repeated indefinitely . to stop converting in the command mode, the master does not acknowledge the final byte of data. this nack stops the ad7091r - 5 transmission, allowing the master to assert a stop condition on the bus. on the receipt of an i 2 c nack condition, the ad7091r - 5 stops converting, but the content of the configuration register is preserved. after the device is re addressed and a read initiated from the conversion result register, the ad7091r - 5 begin s converting on the previously selected sequence of c hannels. the conversion sequence start s at the first selected channel in the sequence. that is, if c hannel 1, channel 2 , and channel 3 are selected and a stop condition occurs after the result for channel 1 is read, on the resumption of conversions, chann el 2 is converted and the conversion sequence continue s . this happens provided the channel register is not written in between conversions . howev er, if the channel register is written, this result s in the conversion starting from c hannel 1.
data sheet ad7091r-5 rev. 0 | page 31 of 34 the example in figure 43 shows command mode converting on a sequence of channels including channel 0, channel 1, and channel 2. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address followed by the write bit (low). 3. the addressed slave device ( ad7091r-5 ) asserts an acknowledge on sda. 4. the master sends the configuration register address (0x02). 5. the slave asserts an acknowledge on sda. 6. the master sends the first data byte (0x03) to the configuration register, which selects the command mode. 7. the slave asserts an acknowledge on sda. 8. the master sends the second data byte (0x00) to the configuration register. 9. the slave asserts an acknowledge on sda. 10. the master sends the channel register address (0x01). 11. the slave asserts an acknowledge on sda. 12. the master sends the data byte (0x07) to the channel register, which selects channel 0, channel 1, and channel 2, followed by a write bit. 13. the slave asserts an acknowledge on sda. 14. the master sends the conversion result register address (0x00). 15. the slave asserts an acknowledge on sda. 16. the master sends a repeated start and the 7-bit slave address followed by the read bit (high). 17. the slave ( ad7091r-5 ) asserts an acknowledge on sda. 18. the master receives a data byte, which contains the channel address bits, the alert bit, and the four msbs of the converted result for channel 0. 19. the master then asserts an acknowledge on sda. 20. the master receives the second data byte, which contains the eight lsbs of the converted result for channel 0. the master then asserts on acknowledge on sda. 21. step 18 to step 20 repeat for channel 1 and channel 2. 22. after the master has received the results from all the selected channels, the slave again converts and outputs the result for the first channel in the selected sequence. step 18 to step 21 are repeated. 23. the master asserts a not acknowledge on sda and a stop condition on sda to end the conversion and exit command mode. to change the conversion sequence, rewrite a new sequence to the command mode. if a new write to the channel register is performed while an existing conversion sequence is underway, the existing conversion sequence is terminated and the next conversion performed is the first selected channel from the new sequence. the maximum throughput that can be achieved using this mode with a 400 khz i 2 c clock is (400 khz/18) = 22.22 ksps. * = position of sampling start from master to slave from slave to master s = start condition sr = repeated start p = stop condition sa = slave acknowledge a = not acknowledge s sa p ... ... 0 sa sa sa command = 0x03 command = 0x00 a ch0[11:8] a point to result reg (0x00) sr 1 sa 0 sa sa ch ad (0000) ... a ch2[11:8] * * * * a a ... ... a ch0[7:0] ... ........ a slave address point to config reg (0x02) ch0[7:0] a ch ad (0001) a ... ch1[7:0] ch1[11:8] ch0[11:8] slave address ch2[7:0] ch2[7:0] ch ad (0010) ch id (0000) ... ... point to channel reg (0x01) sa command = 0x07 12093-062 figure 43. command mode operation
ad7091r-5 data sheet rev. 0 | page 32 of 34 autocycle mode the ad7091r-5 can be configured to convert continuously on a programmable sequence of channels, making it the ideal mode of operation for system monitoring. these conversions occur automatically at intervals chosen by the cycle_timer bits in the configuration register. typically, this mode is used to monitor a selection of channels automatically with the limit registers programmed to signal an out of bounds condition via the alert function. reads and writes can be performed at any time (the conversion result register contains the most recent conversion result). to enter this mode, the required combination of channels that must be monitored is written into the channel register. the required interval between conversions is selected by writing into the cycle_timer bits in the configuration register. autocycle mode operation can then be selected by writing cmd = 0 and auto = 1 in the configuration register. if more than one channel bit is set in the channel register, the adc automatically cycles through the channel sequence, starting with the lowest channel and working its way up through the sequence. after the sequence is complete, the adc starts converting on the lowest channel again, continuing to loop through the sequence until this mode is exited. as soon as a conversion is complete, the conversion result is compared with the content of the limit registers. the alert register is updated automatically with the result of the comparison. if a violation of the limit registers is found, the alert bit in the conversion result register is set and, if the alert/busy/gpo 0 pin functionality is selected in the configuration register, the alert/busy/gpo 0 pin is asserted with the polarity determined by alert_pol_or_gpo0 bit in the configuration register. if an out-of-cycle conversion is required while autocycle mode is active, it is necessary to disable autocycle mode before proceeding to the command or sample mode. when the conversion is complete, the user can reenable autocycle mode. in autocycle mode, the ad7091r-5 does not enter power-down on receipt of a stop condition; therefore, conversions and alert monitoring continues to function. the cycle_timer value in the configuration register controls the time of conversion in autocycle mode. four separate time intervals are available, and each is a multiple of the base_time. the reset value used is 8 base_time. the base time for the ad7091r-5 is approximately 100 s. writing to the channel register or the configuration register when in autocycle mode results in a reset of the cycle timer. this process ensures that the latest information is used for cycle timer calculation. table 25. autocycle interval time command interval time approximate interval 00 1 base_time 100 s (10 ksps) 01 2 base_time 200 s (5 ksps) 10 4 base_time 400 s (2.5 ksps) 11 8 base_time 800 s (1.25 ksps) do not write to the limit and hysteresis registers when the ad7091r-5 is in autocycle mode. if these registers are written by chance, the design stalls the internal cycle timer counters for one scl period when the registers are being updated. a write to the channel register and the configuration register in autocycle mode restarts the cycle timer counters. because the alert indication register is read to clear, read the register only when an alert is indicated. otherwise, there is a risk of inadvertently clearing the alert register and the alert bit in the conversion result register. power-down mode power-down mode is intended for use in applications where slower throughput rates and lower power consumption are required; either the adc is powered down between each conversion, or a burst of conversions can be performed at a higher throughput rate, and the adc is then powered down for a relatively long duration between these bursts of several conversions. when the ad7091r-5 is in power-down mode, all analog circuitry is powered down; however, the serial interface is active. the serial interface of the ad7091r-5 is functional in power- down; therefore, the user may read back the last conversion result even after the device enters power-down mode. to enter power-down, write to the power-down configuration bits in the configuration register, as seen in table 15. to enter full power-down mode, set the sleep mode/bias generator bit to 1, and set the internal reference bit to 0, which ensures that all analog circuitry and the internal reference powers down. when the internal reference is enabled, it consumes power any time bit 0 of the configuration register is set to 1. to exit this mode of operation and power up the ad7091r-5 , set the msb of the p_down word to 1. if a power-up of the internal reference is desired, the p_down lsb must also be set to 1. when using the internal reference, and the device is in full power-down mode, wait to perform conversions until the internal reference has had time to power up and settle. the reference buffer requires 50 ms to power up and charge the 2.2 f decoupling capacitor during the power-up time. after power-up is complete, the adc is fully powered up, and the input signal is properly acquired. to start the next conversion, operate the interface as described in the modes of operation section.
data sheet ad7091r-5 rev. 0 | page 33 of 34 a lert the alert functionality is u sed as an out of bounds indicator. an alert event is triggered when the value in the conversion result register exceeds the chx high limit valu e in the c hannel x high limit register or falls below the chx low limit value in the c hannel x low limit register for a selected channel. detailed alert information is access ible in the alert register. the register contains two status bits per channel, one corresponding to the high limit, and the other to the low limit. a logical or of alert signals for all channels creates a common alert value. this value can be accessed by the alert bit in the conversion result register and configured to drive out on the alert/busy / gpo 0 pin. the alert/busy / gpo 0 pin is configured as an alert output by configuring the follow ing bits in the configuration register: ? set the alert_en_or_gpo0 bit ( bit 4 ) to 1. ? set the busy bit ( bit 5 ) to 0. ? s et the alert_pol_or_gpo0 bit ( bit 3 ) to 0 for the alert/busy/gpo 0 pin to be active low and set it to 1 for the alert/busy/gpo 0 pin to be active high. the alert register, alert bit , and alert/busy/gpo 0 pin are cleared by reading the alert register contents. additionally, i f the conversion result goes beyond the hysteresis value for a selected channel , the alert bit corresponding to t hat channel is reset automatically. issuing a software reset also clear s the alert status. the alert/busy/gpo 0 pin has an open - drain configuration that allows the alert outputs of several ad7091r -5 devices to be wired together when the alert/busy / gpo 0 pin is active low. the alert/busy/gpo 0 pin configuration can be controlled by the alert_drive_type bit, bi t 15 of the configuration register. the alert_pol_or_gpo0 bit (bit 3 of the configuration register) set s the active polarity of the alert output. the power - up default is active low. when using the alert/busy / gpo 0 output pin , an external pull - up resistor is req uired because the output is an open - drain configuration. connect the external pull - up resistor to v drive . the resistor value is application depend ent; however, it must be large enough to avoid excessive sink currents at the alert/busy/gpo 0 output pin. busy when the alert/busy / gpo 0 pin is configured as a busy output, the pin indicate s when a conversion is taking place. the alert/busy / gpo 0 pin is configured as busy by configuring the following bits in the configuration register: ? set the alert_en_or_gpo0 bit, bit 4, to 1. ? set the busy bit, bit 5, to 1. ? set the alert_pol_or_gpo0 bit, bit 3, to 0 for the alert/busy/gpo 0 pin to be active low, and set it to 1 for the alert/busy/gpo 0 pin to be active high. when using the alert/busy/gpo 0 output pin, an external pull - up resistor is required because the output is an open - drain configuration . connect the external pull - up resistor to v drive . the resistor value is application dependent; however, it must be large enoug h to avoid excessive sink currents at the alert/busy/gpo 0 output pin. channel sequencer the ad7091r -5 includes a channel sequencer useful for scanning channels in a repeated fashion. channels included in the sequence are configured in the c hannel r egister. if all the bits in the c hannel re gister are 0, channel 0 is selected by default, and all conversions occur on this channel. if the c hannel r egister is nonzero, the conversion sequence starts from the lowest numbered channel enabled in the c hannel r egister. the sequence cycles through all the enabled channels in ascending order. after all the channels in the sequence are converted, the sequence starts again. there is a latency of one conversion before the channel conversion s equence is updated. if the channel register is programmed with a new value, the conversion sequence is reset to the lowest numbered channel in the new value.
ad7091r-5 data sheet rev. 0 | page 34 of 34 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd. 061609-b bottom view top view exposed pad p i n 1 i n d i c a t o r 4.10 4.00 sq 3.90 seating plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indicator 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 1 20 6 10 11 15 16 5 figure 44. 20-lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp-20-10) dimensions shown in millimeters compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 45. 20-lead thin shrink small outline package [tssop] (ru-20) dimensions shown in millimeters ordering guide model 1 channels temperature range package description package option ad7091r-5bcpz 4 ?40c to +125c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-10 ad7091r-5bcpz-rl7 4 ?40c to +125c 20-lead lead frame chip scale package [lfcsp_wq] cp-20-10 ad7091r-5bruz 4 ?40c to +125c 20-lead thin shrink small outline package [tssop] ru-20 ad7091r-5bruz-rl7 4 ?40c to +125c 20-lead thin shrink small outline package [tssop] ru-20 EVAL-AD7091R-5SDZ evaluation board eval-sdp-cb1z evaluation controller board 1 z = rohs compliant part. i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d12093-0-7/15(0)

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